I validate and characterize hardware at the bench — from PVT corner sweeps and signal integrity analysis to bare-metal firmware on STM32 with statistical methodology and oscilloscope-driven debug. Currently seeking summer internship, co-op, or full-time roles in hardware validation, platform validation, or characterization engineering.
I'm Athish — M.S. Electrical Engineering at Case Western Reserve University. I validate and characterize hardware using oscilloscopes, DMMs, logic analyzers, and bare-metal firmware written at the register level. My work follows semiconductor-industry PVT methodology — every measurement includes sample count, mean, and standard deviation.
Right now I'm running a full platform validation campaign on an STM32F446RE — characterizing GPIO timing determinism, power rail integrity, and communication bus signal quality across voltage corners from 2.8V to 3.6V. I've also built a 5-stage pipelined RISC-V CPU with a custom systolic array coprocessor, hardware-validated on Zynq UltraScale+ at 138 MHz with 36/36 tests passing. Before grad school, I was debugging live transducer signals in a petroleum plant at ONGC — oscilloscope on noisy lines, root-causing grounding faults, calibrating field instruments. That hands-on instinct carries into every bench session.
Looking for a summer internship, Fall 2026 co-op, or full-time role in hardware validation, platform validation, characterization engineering, or system-level test.
M.S. Electrical Engineering · GPA: 3.57/4.0
B.Tech Electronics & Instrumentation · GPA: 3.30/4.0
Hardware Validation · Characterization · Platform Test
Every project below is verified, synthesized, or deployed. The results are real.
A bare-metal multi-sensor data-acquisition platform on the STM32F446RE — a register-level I²C driver for the BME280, a register-level SPI driver for the ADXL345 accelerometer, and CAN 2.0B uplink over an SN65HVD230 transceiver, with a Python host-side visualizer reading telemetry over UART.
A full bench root-cause analysis of an STM32F446RE (Nucleo) transmitting UART at ≈9,800 baud instead of the configured 115,200. On a Keysight InfiniiVision MSO-X 2002A, I cursor-measured the bit period at 102 µs (→ 9,804 baud) and confirmed the line was electrically clean — 3.3 V CMOS, sharp edges, DC-RMS consistent with the 0x55 test pattern — isolating the fault to bit rate rather than signal integrity. Working backward through the USART baud-divider relation, I reverse-engineered the loaded BRR as 0x0683 (the 9,600-baud divisor at a 16 MHz APB2 clock), not the 0x008B required for 115,200 — a firmware constant error, not a silicon defect.
0x0683 to 0x008B (0.08% theoretical error) with an inline derivation comment to kill the magic-number recurrence. Re-measured under identical probe and scope settings, the bit period dropped 102 µs → 9.00 µs — within 3.7% of the theoretical 8.68 µs at 115,200 baud — and the symptom cleared; RCA closed, fix verified. Takeaway: a clean wire is not a correct wire — signal integrity and protocol correctness are independent, and the wire is the source of truth.A bench RCA of a silent fault: USART2 on an STM32F446RE (Nucleo) emitted unreadable serial at 115,200 baud, yet the firmware raised no status flag, no fault exception, and the PA5 heartbeat kept toggling — so any register-based self-check would have passed. Probing MCO1 (SYSCLK/4) on a Keysight DSO-X 2002A, I measured 22.9 MHz against a 45 MHz baseline — an almost exact halving. With PLLM and PLLP confirmed correct, the SYSCLK relation (PLLN sits in the numerator) left only one suspect: RCC_PLLCFGR had PLLN = 180 instead of 360, halving the VCO, SYSCLK (90 vs 180 MHz), and PCLK1 (22.5 vs 45 MHz) — so the unchanged divisor yielded ≈57,600 baud.
PLLN 180→360 brought MCO1 back to ~45 MHz and 115,200-baud output back to readable, with no side effects. To turn this silent class of fault into a detectable one, I specified a boot-time clock self-check (read back RCC_PLLCFGR, recompute SYSCLK, halt on mismatch), a permanent MCO test point, and named clock constants. Resolved and verified — two measurements sharing no common circuitry agreed on the 0.5× factor.A complete SoC — 5-stage pipelined RISC-V processor with the full RV32IM instruction set, zero-penalty data forwarding, load-use stall detection, branch flush, and a custom md_result_captured latch that solves a tricky M-extension pipeline timing hazard.
A real-time embedded surveillance system on Raspberry Pi 5, written in C++17 with OpenCV 4.10. The vision pipeline runs frame differencing plus background subtraction, Gaussian blur, morphological cleanup, and contour scoring to localize motion; a custom StableBox tracker (EMA smoothing α=0.15, 10 px deadzone, 15% per-frame size clamp, 3-frame confirmation) suppresses jitter from low-cost USB cameras. A Moore finite-state machine sorts activity into four severity levels and switches recording mode accordingly — idle logging, low-res JPEG, high-res JPEG, and MJPG video — with immediate escalation but hysteresis-delayed de-escalation to stop mode flicker.
A research project exploring hafnium-oxide-based ferroelectric architectures — FeRAM, FeFET, and NCFET — for next-generation non-volatile memory and steep-slope logic applications. Covers material physics, phase transitions, polarization mechanisms, and CMOS fabrication compatibility.
Designed a streaming datapath computing y = (a×b) + (c×d) + e on signed 16-bit fixed-point inputs with a valid-ready handshake interface. Built both an unpipelined single-cycle version and a parameterized pipelined version with configurable depth (2–5 stages).
Three compute modes — sequential MAC, 4-way parallel MAC with an adder tree, and early-exit with a magnitude comparator. Controlled by a 5-state hybrid Moore/Mealy FSM with stall handling, output backpressure, and built-in hardware performance counters.
Modeled a one-dimensional abrupt p-n junction using COMSOL Multiphysics. Simulated electrostatic potential, electron/hole concentration profiles, net charge density, and electric field under equilibrium, forward bias (0 to +0.5 V), and reverse bias (0 to −1.5 V). Parametric sweep over donor concentration ND ∈ {1, 2, 5} × 10¹⁶ cm⁻³.
Extended the 1D model to a full 2D p-i-n junction (12×6 µm) solved via coupled drift-diffusion PDEs in COMSOL. Studied photodetector and solar-cell behavior by sweeping optical generation rate G₀ under zero and −2 V reverse bias. Derived the logarithmic scaling of quasi-Fermi level splitting: ΔEf ≈ 2Vt · ln(G₀τ / nᵢ).
MATLAB programming assignments on the kinematics of the 6-DOF Intelledex serial manipulator, built on screw theory and homogeneous transforms. PA 1 implements forward kinematics two independent ways — Product of Exponentials (matrix exponentials of se(3) twists) and Denavit–Hartenberg — which agree on end-effector position and both produce valid SE(3) transforms (orthonormal R, det ≈ +1). PA 2 solves analytical inverse kinematics by Paden–Kahan subproblem decomposition (subproblems 1–3), then verifies the recovered joint angles by feeding them back through the PoE forward model. PA 3 computes the spatial and body Jacobians via the adjoint map and uses the Jacobian rank and its null spaces to flag singular configurations — separating internal joint motions that don't move the tool from end-effector twists the arm can't produce.
Designed and optimized two fundamental neural-network layers — a fully-connected (linear) layer and a 2D convolution layer — in Xilinx Vitis HLS, using INT8 operands with INT32 accumulation on a Zynq UltraScale+ (xczu3eg) at 100 MHz. Benchmarked pragma-free baselines against variants tuned with PIPELINE, UNROLL, and ARRAY_PARTITION directives.
A complete Transformer block — multi-head self-attention, MLP, LayerNorm, and softmax — written in C++ and synthesized to RTL with Vitis HLS, then placed-and-routed and run on the Avnet AUP-ZU3 (Zynq UltraScale+ ZU3EG). Two variants share an identical activation datapath but differ in the six weight-projection layers: a 16-bit fixed-point baseline versus a BitNet-style ternary {−1,0,+1} design that replaces every weight multiply with a conditional add/subtract/zero, freeing the device's DSP slices for the activation-times-activation matmuls.
ap_fixed weights all plateau at 33 DSPs because Vitis HLS maps any product fitting the DSP48E2's 27×18 multiplier onto a single DSP — so on FPGAs, precision narrowing buys BRAM but not DSP; only the ternary operator replacement releases DSP capacity.Built a 2D electrostatic model of a MOS capacitor and an n-channel MOSFET in COMSOL's Electrostatics interface, solving Poisson's equation with Boltzmann carrier statistics and a hand-defined space-charge density. Part 1 sweeps gate voltage (−2 to +5 V), substrate doping (10¹⁵–10¹⁸ cm⁻³), and oxide thickness (10–100 nm), extracting depth profiles of potential, carrier concentration, electric field, and net charge. Part 2 adds n⁺ source/drain and maps the 2D potential and electron density across (VGS, VDS) bias points.
A hand-soldered analog signal conditioning circuit — op-amp gain stage plus LDR voltage divider — interfaced to an 8051 microcontroller via ADC. Built for fluid-level detection in medical IV bottles.
A remote monitoring system that publishes sensor data over MQTT with TLS encryption to AWS IoT. Supports actuator control through cloud-triggered GPIO callbacks and I²C sensor interfacing.
A Wi-Fi-enabled notice board that receives messages through a web interface and displays them on an LCD screen in real time. Uses ThingSpeak for cloud-based logging.
A closed-loop fan speed controller built with an Arduino and an LM35 temperature sensor. PWM-regulated. Hand-soldered on a breadboard.
The tools, languages, and platforms I use to design, simulate, build, and debug.
M.S. Electrical Engineering
B.Tech Electronics & Instrumentation
I'm actively looking for summer internship, co-op, or full-time opportunities in hardware validation, platform validation, characterization engineering, or system-level test. Based in Cleveland, OH — happy to chat about any role that involves bench work, oscilloscopes, and quantitative hardware characterization.