I design and build hardware — from pipelined RISC-V processors validated on a real FPGA to register-level firmware on STM32 with FreeRTOS and CAN bus. Currently seeking co-op roles where I can contribute to a real hardware or firmware team.
I'm Athish — M.S. Electrical Engineering at Case Western Reserve University. I work across the full hardware stack, from bare-metal firmware on ARM Cortex-M to pipelined processor design in SystemVerilog on Xilinx FPGAs.
At CWRU, I designed a 5-stage pipelined RISC-V CPU with a custom systolic array coprocessor and validated it on real Zynq UltraScale+ silicon — 138 MHz, 4,777 LUTs, 36/36 tests passing, correct output confirmed on board LEDs. Right now I'm building register-level I2C and SPI drivers on an STM32F446RE with CAN bus and FreeRTOS — no libraries, just datasheets and registers. Before grad school, I was at Manipal Institute of Technology building 8051-based medical monitors, ESP32 IoT systems, and hand-soldering analog circuits. That's where I figured out I wanted to work in hardware — not just study it.
Looking for a Fall 2026 co-op in hardware engineering, embedded firmware, FPGA design, or anything where the work ends up on a board or in silicon.
M.S. Electrical Engineering · GPA: 3.25/4.0
B.Tech Electronics & Instrumentation · GPA: 3.30/4.0
Hardware · Embedded · FPGA · Firmware
Every project below is verified, synthesized, or deployed. The results are real.
A complete SoC — 5-stage pipelined RISC-V processor with the full RV32IM instruction set, zero-penalty data forwarding, load-use stall detection, branch flush, and a custom md_result_captured latch that solves a tricky M-extension pipeline timing hazard.
Register-level I2C driver for BME280, register-level SPI driver for ADXL345 accelerometer, CAN 2.0B transmission via SN65HVD230. FreeRTOS managing four concurrent tasks through queues and mutexes. Python host-side visualization via UART. No HAL, no Arduino — datasheets and peripheral registers.
An event-driven surveillance system running on a Raspberry Pi. A 4-state finite state machine classifies motion into four activity levels using frame-differencing and adaptive thresholds, then automatically adjusts the recording mode.
A research project exploring hafnium-oxide-based ferroelectric architectures — FeRAM, FeFET, and NCFET — for next-generation non-volatile memory and steep-slope logic applications. Covers material physics, phase transitions, polarization mechanisms, and CMOS fabrication compatibility.
Designed a streaming datapath computing y = (a×b) + (c×d) + e on signed 16-bit fixed-point inputs with a valid-ready handshake interface. Built both an unpipelined single-cycle version and a parameterized pipelined version with configurable depth (2–5 stages).
Three compute modes — sequential MAC, 4-way parallel MAC with an adder tree, and early-exit with a magnitude comparator. Controlled by a 5-state hybrid Moore/Mealy FSM with stall handling, output backpressure, and built-in hardware performance counters.
Modeled a one-dimensional abrupt p-n junction using COMSOL Multiphysics. Simulated electrostatic potential, electron/hole concentration profiles, net charge density, and electric field under equilibrium, forward bias (0 to +0.5 V), and reverse bias (0 to −1.5 V). Parametric sweep over donor concentration Nₐ ∈ {1, 2, 5} × 10¹⁶ cm⁻³.
Extended the 1D model to a full 2D p-i-n junction (12×6 µm) solved via coupled drift-diffusion PDEs in COMSOL. Studied photodetector and solar-cell behavior by sweeping optical generation rate G₀ under zero and −2 V reverse bias. Derived the logarithmic scaling of quasi-Fermi level splitting: ΔEf ≈ 2Vt · ln(G₀τ / nᵢ).
A hand-soldered analog signal conditioning circuit — op-amp gain stage plus LDR voltage divider — interfaced to an 8051 microcontroller via ADC. Built for fluid-level detection in medical IV bottles.
A remote monitoring system that publishes sensor data over MQTT with TLS encryption to AWS IoT. Supports actuator control through cloud-triggered GPIO callbacks and I²C sensor interfacing.
A Wi-Fi-enabled notice board that receives messages through a web interface and displays them on an LCD screen in real time. Uses ThingSpeak for cloud-based logging.
A closed-loop fan speed controller built with an Arduino and an LM35 temperature sensor. PWM-regulated. Hand-soldered on a breadboard.
The tools, languages, and platforms I use to design, simulate, build, and debug.
M.S. Electrical Engineering
B.Tech Electronics & Instrumentation
I'm actively looking for Fall 2026 co-op opportunities in FPGA design, embedded systems, firmware, and hardware engineering. Based in Cleveland, OH — happy to chat about any role that involves building real hardware.